Understanding and Mitigating UBM Stack Failures in Compound Semiconductor Manufacturing

A $30,000 module fails board-level assembly.
The root cause is a 10–15% variation in a 400–850 nm Ti/Ni/Au stack.

Three pockets. Sequential deposition. Lift-off.

→ Ti for adhesion
→ Ni for diffusion barrier
→ Au for solder wettability

That stack is one of the thinnest in compound semiconductor manufacturing, and one of the most critical.

It’s the last thing deposited before dicing, and the first thing blamed six months later when a device fails ball-lift.

The compound semiconductor chiplet push is accelerating.

DARPA has committed $420M to heterogeneous integration. The CHIPS Act funded MACOM to scale GaN to 150 mm for advanced packaging. The DoD has allocated $560M toward domestic packaging and integration.

Every one of those chiplets relies on this UBM stack, and the failure mode is consistent:

• The Ti adhesion layer isn’t uniform. Not catastrophically, just thinner at the wafer edge.
• Every chiplet from that zone carries reduced adhesion.
• The system geometry put them there.

Two things determine whether that happens:

First: whether every wafer sees the same time-averaged flux from the e-beam source, uniformity driven by motion geometry, not masking.

Second: whether each pocket is properly isolated during deposition. Even minor Ni contamination in the Ti layer disrupts the adhesion chemistry that the stack depends on.

Beyond optimization, these are yield gates on eight-figure programs.

CS MANTECH is happening May 18–21 in Portland.
Come talk to us at Ferrotec (Thin Film Solutions Group), Booth 214.

Northrop Grumman| RTX | MACOM | Qorvo, Inc. | imec | BAE Systems

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